Power circuits have been used in various electronic circuits to convert incoming electrical signals to a desired voltage type (e.g., alternating current (AC), direct current (DC), etc.). Circuits capable of converting signals into DC by controlling on/off-time of semiconductor switches are increasingly becoming more important. These circuits can be brought to a halt (or dormant) mode when the operation mode of a controlling CPU (which implements power feeding) is switched to a low current consuming state, in which a relatively small amount of current flows in the circuit.
Under this halt mode, the operation mode, in which the semiconductors switch as a chopper unit, is switched to the “always-on” state so as to raise the output voltage, whereby the on/off control unit of the semiconductor switch in the power circuit is halted and the amount of power consumed by the control unit is reduced.
FIG. 6 illustrates a schematic diagram of a known DC converter C3 provided with the above-mentioned halt mode. The DC converter C3 includes at least a DC chopper circuit 100, a drive circuit 200 for switching the DC chopper circuit 100 from regular operation mode to halt mode, and a current limiter 300 for preventing the flow of over-current through respective circuit elements included in the DC chopper circuit 100.
The DC chopper circuit 100 is formed using a P-channel type MOSFET as a semiconductor switch 1, with a source terminal receiving a source voltage VDDB; a diode 2 connected to the drain terminal of P-channel type MOSFET 1, a reactance inductor 3, a capacitor 4 for voltage output, and a signal generator 5 for generating pulse width modulation (PWM) clock signals to be utilized for controlling the on/off time of semiconductor switch 1 so that a constant output voltage Vout is obtained. This signal generator is hereinafter referred to as clock generator 5.
If a halt mode set-up signal is at the low level, the drive circuit 200 shown in FIG. 6 alternately switches the voltage of the signals PHS output from point A to high (HI) and low (LO) levels by turning on pMOS 205 and nMOS 210, respectively, according to PWM clock signals input by the clock generator 5.
In this case, the drive circuit 200 operates such that both MOS transistors 205, 210 are required to be in an off-state before one of them is subsequently turned on. The PHS output from point A of drive circuit 200 is then applied to the gate of the semiconductor switch 1 in the DC chopper circuit 100. In addition, when the halt mode set-up signal is switched from LO to HI, the drive circuit 200 operates to output HI and LO signals to pMOS 205 and nMOS 210, respectively, regardless of the level of the clock signals output from clock generator 5. The semiconductor switch 1 in DC chopper circuit 100 is therefore brought to the always-off state, at which point the current limiter 300 initiates its operation.
However, since the transistors used as the semiconductor switch 1 are typically of a low-current (i.e., slow response) type, the circuit is particularly susceptible to over-current conditions.
For the sake of simplicity, further detail regarding the operation of the drive circuit 200 will be abbreviated since they are well-known to those skilled in the art.
The current limiter 300 includes a comparison unit for detecting drain current of the semiconductor switch 1 and comparing the detected drain current with a predetermined current value. A switch unit switches the semiconductor switch 1 to the off-state when the drain current exceeds the predetermined current value by outputting HI signals to the gate of semiconductor switch 1. The switch unit switches the semiconductor switch 1 regardless of the signals output from drive circuit 200, which provides an output based on the output of the comparison unit at the moment when the drain current exceeds the predetermined current value. The on/off control from the drive circuit 200 is triggered when the drain current falls below the predetermined current value by outputting LO signals to the gate of semiconductor switch 1. In order to reduce the current consumed in the current limiter 300 under an emergency measure, the semiconductors of a low current consuming type, or slow response type, have been used for forming the switch unit, as described above.
When the semiconductor switch in the DC chopper unit is in either the high (HI) or low (LO) level in the noted DC converter C3, the halt mode set-up signal is switched from the low (LO) to high (HI) level and then the signal PHS is output from the point A of the drive circuit 200.
FIG. 7A illustrates the change in the output voltage Vout over time, as well as the drain current, and the voltage PHS applied to the gate of semiconductor switch 1, when the semiconductor switch in the DC chopper unit 100 is in the on-state and the halt mode set-up signal is switched from LO to HI. The drawing plots the voltage (V) and current (A), vertically, over time (μs), in which the time, 0 (μs), corresponds to the instant the halt mode set-up signal is switched from LO to HI. Since the resistance is relatively small for the semiconductor switch 1 in the on-state and considerably small for the inductor 3, the over-current causes current to flow into the output capacitor 4 as soon as the semiconductor switch 1 is switched to the continuous-on state, regardless of the clock signals.
As illustrated in FIG. 7A, the current flowing through semiconductor switch 1 increases rapidly over time to reach its maximum of approximately 2A after around 20 μs. As noted earlier, if the amount of the drain current exceeds a predetermined value, the current limiter 300 limits the PHS voltage to bring semiconductor switch 1 into the off-state. However, since the transistors in the current limiter 300 are of a low current consuming type, or slow responding type, when the semiconductor switches to reduce the normal current consumption, the occurrence of the over-current remains a problem.
FIG. 7B illustrates the characteristics of the output voltage Vout, the drain current, and the voltage PHS applied to the gate of semiconductor switch 1 over time when the semiconductor switch 1 included in DC chopper circuit 100 has been completely turned off and the halt mode set-up signal is switched from LO to HI.
Typically, a predetermined period of time (such as 50 μs, for example) will pass before the semiconductor switch 1, which has been turned off previously, switches on again. This period of time allows the current limiter 300, formed with the semiconductor switches of slow driving capability, to adequately respond to the switching behavior of the circuit without causing the noted over-current. In addition, if the current limiter 300 is formed with semiconductor switches having the driving capability suitable for responding to the switching, the increase in size of the semiconductor elements will not be as great.
As illustrated in FIG. 7B, the drain current of the semiconductor switch 1 starts increasing approximately after 80 μs and the current limiter 300 starts properly functioning after about 100 μs, whereby the occurrence of the over-current can be prevented. When the system is set to the halt mode during the on-state period of the semiconductor switch 1, the starting of proper operation for the current limiter 300 is delayed for a certain period of time, thereby causing a momentous flow of over-current.
As one of the measures to alleviate the over-current, the current limiter 300 may be formed with semiconductor switches of high driving capability, i.e., fast responding. This measure, however, may result in undue increase in current consumption as well as production costs.